Palladium gates for reproducible quantum dots in silicon

We replace the established aluminium gates for the formation of quantum dots in silicon with gates made from palladium. We study the morphology of both aluminium and palladium gates with transmission electron microscopy. The native aluminium oxide is found to be formed all around the aluminium gates, which could lead to the formation of unintentional dots. Therefore, we report on a novel fabrication route that replaces aluminium and its native oxide by palladium with atomic-layer-deposition-grown aluminium oxide. Using this approach, we show the formation of low-disorder gate-defined quantum dots, which are reproducibly fabricated. Furthermore, palladium enables us to further shrink the gate design, allowing us to perform electron transport measurements in the few-electron regime in devices comprising only two gate layers, a major technological advancement. It remains to be seen, whether the introduction of palladium gates can improve the excellent results on electron and nuclear spin qubits defined with an aluminium gate stack

Depletion-mode Quantum Dots in Intrinsic Silicon

We report the fabrication and electrical characterization of depletion-mode quantum dots in a two-dimensional hole gas (2DHG) in intrinsic silicon. We use fixed charge in a SiO$_2$/Al$_2$O$_3$ dielectric stack to induce a 2DHG at the Si/SiO$_2$ interface. Fabrication of the gate structures is accomplished with a single layer metallization process. Transport spectroscopy reveals regular Coulomb oscillations with charging energies of 10-15 meV and 3-5 meV for the few- and many-hole regimes, respectively. This depletion-mode design avoids complex multilayer architectures requiring precision alignment, and allows to adopt directly best practices already developed for depletion dots in other material systems. We also demonstrate a method to deactivate fixed charge in the SiO$_2$/Al$_2$O$_3$ dielectric stack using deep ultraviolet light, which may become an important procedure to avoid unwanted 2DHG build-up in Si MOS quantum bits.Comment: Accepted to Applied Physics Letters. 5 pages, 3 figure

Reducing charge noise in quantum dots by using thin silicon quantum wells

Charge noise in the host semiconductor degrades the performance of spin-qubits and poses an obstacle to control large quantum processors. However, it is challenging to engineer the heterogeneous material stack of gate-defined quantum dots to improve charge noise systematically. Here, we address the semiconductor-dielectric interface and the buried quantum well of a 28 Si/SiGe heterostructure and show the connection between charge noise, measured locally in quantum dots, and global disorder in the host semiconductor, measured with macroscopic Hall bars. In 5 nm thick 28 Si quantum wells, we find that improvements in the scattering properties and uniformity of the two-dimensional electron gas over a 100 mm wafer correspond to a significant reduction in charge noise, with a minimum value of 0.29 ± 0.02 μeV/Hz ½ at 1 Hz averaged over several quantum dots. We extrapolate the measured charge noise to simulated dephasing times to -gate fidelities that improve nearly one order of magnitude. These results point to a clean and quiet crystalline environment for integrating long-lived and high-fidelity spin qubits into a larger system. Charge noise degrades the performance of spin qubits hindering scalability. Here the authors engineer the heterogeneous material stack in 28 Si/SiGe gate-defined quantum dots, to improve the scattering properties and to reduce charge noise

A fabrication guide for planar silicon quantum dot heterostructures

We describe important considerations to create top-down fabricated planar quantum dots in silicon, often not discussed in detail in literature. The subtle interplay between intrinsic material properties, interfaces and fabrication processes plays a crucial role in the formation of electrostatically defined quantum dots. Processes such as oxidation, physical vapor deposition and atomic-layer deposition must be tailored in order to prevent unwanted side effects such as defects, disorder and dewetting. In two directly related manuscripts written in parallel we use techniques described in this work to create depletion-mode quantum dots in intrinsic silicon, and low-disorder silicon quantum dots defined with palladium gates. While we discuss three different planar gate structures, the general principles also apply to 0D and 1D systems, such as self-assembled islands and nanowires.Comment: Accepted for publication in Nanotechnology. 31 pages, 12 figure

Author Correction : Reducing charge noise in quantum dots by using thin silicon quantum wells

The original version of this Article omitted fromthe author list the author Amir Sammakwho is from the 'QuTech and Netherlands Organisation for Applied Scientific Research (TNO), Delft, The Netherlands'. This has been corrected in both the PDF and HTML versions of the Article

Low disorder and high valley splitting in silicon

The electrical characterisation of classical and quantum devices is a critical step in the development cycle of heterogeneous material stacks for semiconductor spin qubits. In the case of silicon, properties such as disorder and energy separation of conduction band valleys are commonly investigated individually upon modifications in selected parameters of the material stack. However, this reductionist approach fails to consider the interdependence between different structural and electronic properties at the danger of optimising one metric at the expense of the others. Here, we achieve a significant improvement in both disorder and valley splitting by taking a co-design approach to the material stack. We demonstrate isotopically-purified, strained quantum wells with high mobility of 3.14(8)$\times$10$^5$ cm$^2$/Vs and low percolation density of 6.9(1)$\times$10$^{10}$ cm$^{-2}$. These low disorder quantum wells support quantum dots with low charge noise of 0.9(3) $\mu$eV/Hz$^{1/2}$ and large mean valley splitting energy of 0.24(7) meV, measured in qubit devices. By striking the delicate balance between disorder, charge noise, and valley splitting, these findings provide a benchmark for silicon as a host semiconductor for quantum dot qubits. We foresee the application of these heterostructures in larger, high-performance quantum processors

A highly pH-sensitive nanowire field-effect transistor based on silicon on insulator

Background: An experimental and theoretical study of a silicon-nanowire field-effect transistor made of silicon on insulator by CMOS-compatible methods is presented.Results: A maximum Nernstian sensitivity to pH change of 59 mV/pH was obtained experimentally. The maximum charge sensitivity of the sensor was estimated to be on the order of a thousandth of the electron charge in subthreshold mode.Conclusion: The sensitivity obtained for our sensor built in the CMOS-compatible top-down approach does not yield to the one of sensors built in bottom-up approaches. This provides a good background for the development of CMOS-compatible probes with primary signal processing on-chip

Reducing charge noise in quantum dots by using thin silicon quantum wells

Charge noise degrades the performance of spin qubits hindering scalability. Here the authors engineer the heterogeneous material stack in 28Si/SiGe gate-defined quantum dots, to improve the scattering properties and to reduce charge noise